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    <meta name="description" content="语言概述Verilog-AMS语言是一种高层次的模块化硬件描述语言，它用模块的形式来描述模拟系统及其子系统的结构和行为。Verilog-AMS语言可分为数字电路描述子集Verilog-HDL和模拟电路描述子集Verilog-A。 Verilog-AMS语言对模拟电路的描述可以分成两种类型：行为描述与结构描述。  行为描述是指用一些数学表达式或者传输函数来描述目标电路的行为，其描述范围可以从基本的电">
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    <div class="post-body" itemprop="articleBody"><h2 id="语言概述"><a href="#语言概述" class="headerlink" title="语言概述"></a>语言概述</h2><p>Verilog-AMS语言是一种高层次的模块化硬件描述语言，它用模块的形式来描述模拟系统及其子系统的结构和行为。Verilog-AMS语言可分为数字电路描述子集Verilog-HDL和模拟电路描述子集Verilog-A。</p>
<p>Verilog-AMS语言对模拟电路的描述可以分成两种类型：行为描述与结构描述。</p>
<ul>
<li>行为描述是指用一些数学表达式或者传输函数来描述目标电路的行为，其描述范围可以从基本的电阻、电容到十分复杂的滤波器或其他模拟系统；</li>
<li>结构描述则是对各个子模块在系统中 的用途以及子模块与子模块之间的连接关系进行描述，这可以理解为是对系统结构框图的描述。完整的结构描述需要包括对信号、端口和基本参数的定义。</li>
</ul>
<p><img src="/blog/../../images/Verilog-ams/image-20230910163108734.png" alt="image-20230910163108734">                                </p>
<p>Verilog-Ams的行为模为模式如下图所示：</p>
<p><img src="/blog/../../images/Verilog-ams/image-20230910165831667.png" alt="image-20230910165831667"></p>
<ul>
<li>Verilog-AMS是由模块构成的，每个模块的内容都镶嵌在<code>module</code>-<code>endmodule</code> 两个语句之间，每个模块实现特定的功能，模块可以进行层次嵌套；</li>
<li>Verilog-AMS的行为建模，关于模拟电路部分(即<strong>Verilog-A</strong>)使用的是<code>analog</code>关键字，关于数字电路部分(即<strong>Verilog</strong>)则用的是<code>always 和 initial</code>。</li>
</ul>
<p><strong>注：没有在Verilog-HDL中出现的新东西，自动认为是属于Verilog-A的部分</strong></p>
<span id="more"></span>

<h2 id="数据类型"><a href="#数据类型" class="headerlink" title="数据类型"></a>数据类型</h2><p>Verilog-AMS 支持 Verilog HDL 中的<code>integer</code>、<code>real</code>以及<code>parameter</code> 数据类型。</p>
<figure class="highlight plaintext"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br></pre></td><td class="code"><pre><span class="line">integer num = 10; // 单个的整型变量 </span><br><span class="line">integer flag [7:0]; // 8个整数组成的数组 </span><br><span class="line">real pi = 3.1415926; // 单个的实数型变量</span><br><span class="line">parameter real tc = 1.5m from (0:3m);</span><br></pre></td></tr></table></figure>

<p>但是，和 Verilog-HDL 使用<code>parameter</code>类型的中有所不同，<strong>Verilog-AMS拓宽了<code>parameter</code> 类型在模拟电路中的功能</strong>：</p>
<ul>
<li>在 Verilog-HDL中，<code>parameter</code> 类型的变量是常数，一旦被定义并分配了初始值，就不能在模拟过程中改变它们的值。</li>
<li>在Verilog-A中，参数的默认值可以在模拟电路的不同部分或不同阶段中根据需要进行更改，以适应不同的仿真条件或电路行为。定义参数的范围，是为了确保参数的取值在模拟中是合理的，以避免出现不合理的模拟结果或错误。</li>
</ul>
<p>在Verilog-AMS中，一个模块如果包含端口，那么必须进行端口说明。端口必须具有一定的类型和方向。Verilog-AMS语句可以描述很多的守恒系统和信号流程系统，例如电磁流体力学和热力学系统等等。因此，在Verilog-AMS模型中，端口也具有多种类型。</p>
<p>其中，在电学特性中，有电压型<code>voltage</code>、电流型<code>current</code>或者同时具有两种特性<code>electrical</code>。对于常用的<code>electrical</code>类型，需要用到数据类型 <code>discipline</code>。</p>
<p> <code>discipline</code>类型， 用于定义自定义的仿真控制规则，其使用方法如下：</p>
<figure class="highlight plaintext"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br><span class="line">5</span><br><span class="line">6</span><br><span class="line">7</span><br><span class="line">8</span><br><span class="line">9</span><br><span class="line">10</span><br><span class="line">11</span><br><span class="line">12</span><br><span class="line">13</span><br><span class="line">14</span><br><span class="line">15</span><br><span class="line">16</span><br></pre></td><td class="code"><pre><span class="line">module my_discipline;</span><br><span class="line">  // 定义一个 discipline 变量</span><br><span class="line">  discipline my_discipline_var &#123;</span><br><span class="line">    real voltage across;</span><br><span class="line">    real current through;</span><br><span class="line">  &#125; my_discipline_instance;</span><br><span class="line">  </span><br><span class="line">  // discipline 方法，用于定义仿真规则</span><br><span class="line">  method void initialize() &#123;</span><br><span class="line">    // 初始化代码</span><br><span class="line">  &#125;</span><br><span class="line">  </span><br><span class="line">  method void post_solve() &#123;</span><br><span class="line">    // 后处理代码</span><br><span class="line">  &#125;</span><br><span class="line">endmodule</span><br></pre></td></tr></table></figure>

<p><code>discipline</code>类似于面向对象编程的<code>class</code>，用 <code>discipline</code> 关键字来定义一个叫 <code>electrical</code> 的「类」，通过<code>electrical</code>定义的<strong>对象</strong>，在电路中就相对于一个节点。</p>
<h2 id="运算符与表达式"><a href="#运算符与表达式" class="headerlink" title="运算符与表达式"></a>运算符与表达式</h2><p>Verilog-A支持Verilog中的<strong>常规运算符</strong>，如<code>+ * %  / </code>， 并且优先级一致。</p>
<p>Verilog-A内置<strong>常规表达式</strong>，用来提供一些数学运算功能，例如<code>sin(x); ln(x); exp(x); pow(x, y)</code>，和模拟电路中常用的物理量</p>
<figure class="highlight plaintext"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br></pre></td><td class="code"><pre><span class="line">$realtime; // Current simulation time in seconds.</span><br><span class="line">$temperature; // Ambient temperature in kelvin. </span><br><span class="line">$vt Thermal; // voltage (kT/q). </span><br><span class="line">$vt(temp); // Thermal voltage at given temperature.</span><br></pre></td></tr></table></figure>

<p>Verilog-A提供<strong>模拟信号访问函数</strong>，用来访问两个节点间的电压，例如<code>V(x,y)</code>和<code>I(x,y)</code></p>
<p>为了便于实现模拟电路系统性能与物理实现之间的优化设计，方便定义输入与输出信号之间的数学函数关系，Verilog-AMS提供了多层次的行为和结构模型及多种<strong>行为模块描述函数</strong>：</p>
<ul>
<li>时间积分函数idt()</li>
<li>时间微分函数ddt()</li>
<li>转换整形函数slew()</li>
<li>拉普拉斯变换函 数laplace zp()</li>
<li>延迟函数delay()</li>
</ul>
<p>Verilog-A将对模拟信号赋值的运算符称为<strong>模拟运算符</strong>，写作<code>&lt;+</code> ，该运算符只能用在<code>analog begin ... end</code>的行为描述中，例如：</p>
<figure class="highlight plaintext"><table><tr><td class="gutter"><pre><span class="line">1</span><br></pre></td><td class="code"><pre><span class="line">V(a, b) &lt;+ R * I(a, b); // 赋予节点a和b之间一个电阻特性，阻值为R。（相当于在节点a和b之间定义了一个阻值为R的电阻）</span><br></pre></td></tr></table></figure>



<h2 id="使用方法"><a href="#使用方法" class="headerlink" title="使用方法"></a>使用方法</h2><h3 id="电阻和电导"><a href="#电阻和电导" class="headerlink" title="电阻和电导"></a>电阻和电导</h3><figure class="highlight verilog"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br><span class="line">5</span><br><span class="line">6</span><br><span class="line">7</span><br><span class="line">8</span><br><span class="line">9</span><br><span class="line">10</span><br><span class="line">11</span><br><span class="line">12</span><br></pre></td><td class="code"><pre><span class="line"><span class="comment">// Linear resistor(resistance formulation)</span></span><br><span class="line"><span class="meta">`<span class="keyword">include</span> &quot;disciplines.v&quot;</span></span><br><span class="line"></span><br><span class="line"><span class="keyword">module</span> resistor(p, n);</span><br><span class="line">	<span class="keyword">parameter</span> <span class="keyword">real</span> r = <span class="number">0</span>; <span class="comment">// resistance(Ohms)</span></span><br><span class="line">	<span class="keyword">inout</span> p, n;</span><br><span class="line">	electrical P, n;</span><br><span class="line">    </span><br><span class="line">	analog <span class="keyword">begin</span></span><br><span class="line">    	V(p, n) &lt;+ r * I(p, n);</span><br><span class="line">	<span class="keyword">end</span></span><br><span class="line"><span class="keyword">endmodule</span></span><br></pre></td></tr></table></figure>



<figure class="highlight verilog"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br><span class="line">5</span><br><span class="line">6</span><br><span class="line">7</span><br><span class="line">8</span><br><span class="line">9</span><br><span class="line">10</span><br><span class="line">11</span><br><span class="line">12</span><br></pre></td><td class="code"><pre><span class="line"><span class="comment">// Linear conductor(conductance formulation)</span></span><br><span class="line"><span class="meta">`<span class="keyword">include</span> &quot;disciplines.v&quot;</span></span><br><span class="line"></span><br><span class="line"><span class="keyword">module</span> conductor(p, n);</span><br><span class="line">	<span class="keyword">parameter</span> <span class="keyword">real</span> g =<span class="number">0</span>； <span class="comment">// conductance(Simens)</span></span><br><span class="line">	<span class="keyword">inout</span> p, n;</span><br><span class="line">	electrical p, n;</span><br><span class="line">    </span><br><span class="line">	analog <span class="keyword">begin</span></span><br><span class="line">        I(p, n) &lt;+ g*V(p, n);</span><br><span class="line">    <span class="keyword">end</span></span><br><span class="line"><span class="keyword">endmodule</span></span><br></pre></td></tr></table></figure>

<h3 id="电容和电感"><a href="#电容和电感" class="headerlink" title="电容和电感"></a>电容和电感</h3><figure class="highlight verilog"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br><span class="line">5</span><br><span class="line">6</span><br><span class="line">7</span><br><span class="line">8</span><br><span class="line">9</span><br><span class="line">10</span><br><span class="line">11</span><br><span class="line">12</span><br></pre></td><td class="code"><pre><span class="line"><span class="comment">// Linear capacitor</span></span><br><span class="line"><span class="meta">`<span class="keyword">include</span> &quot;disciplines.v&quot;</span></span><br><span class="line"></span><br><span class="line"><span class="keyword">module</span> capacitor(p, n)；</span><br><span class="line">	<span class="keyword">parameter</span> <span class="keyword">real</span> c = <span class="number">0</span>; <span class="comment">// capacitance(F)</span></span><br><span class="line">	<span class="keyword">inout</span> p, n;</span><br><span class="line">	electrical p, n;</span><br><span class="line">    </span><br><span class="line">	analog <span class="keyword">begin</span></span><br><span class="line">        I(p, n) &lt;+ c*ddt(V(p，n));</span><br><span class="line">    <span class="keyword">end</span></span><br><span class="line"><span class="keyword">endmodule</span></span><br></pre></td></tr></table></figure>

<figure class="highlight verilog"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br><span class="line">5</span><br><span class="line">6</span><br><span class="line">7</span><br><span class="line">8</span><br><span class="line">9</span><br><span class="line">10</span><br><span class="line">11</span><br><span class="line">12</span><br></pre></td><td class="code"><pre><span class="line"><span class="comment">// Linear inductor</span></span><br><span class="line"><span class="meta">`<span class="keyword">include</span> &quot;disciplines.v&quot;</span></span><br><span class="line"></span><br><span class="line"><span class="keyword">module</span> inductor(p,n);</span><br><span class="line">	<span class="keyword">parameter</span> <span class="keyword">real</span> l = <span class="number">0</span>; <span class="comment">// inductance(H)</span></span><br><span class="line">	<span class="keyword">inout</span> p,n;</span><br><span class="line">	electrical p, n;</span><br><span class="line">	</span><br><span class="line">    analog <span class="keyword">begin</span></span><br><span class="line">        V(p, n) &lt;+ l*ddt(I(p,n));</span><br><span class="line">    <span class="keyword">end</span></span><br><span class="line"><span class="keyword">endmodule</span></span><br></pre></td></tr></table></figure>

<h3 id="电压源和电流源"><a href="#电压源和电流源" class="headerlink" title="电压源和电流源"></a>电压源和电流源</h3><figure class="highlight verilog"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br><span class="line">5</span><br><span class="line">6</span><br><span class="line">7</span><br><span class="line">8</span><br><span class="line">9</span><br><span class="line">10</span><br><span class="line">11</span><br><span class="line">12</span><br><span class="line">13</span><br><span class="line">14</span><br><span class="line">15</span><br><span class="line">16</span><br><span class="line">17</span><br><span class="line">18</span><br><span class="line">19</span><br><span class="line">20</span><br><span class="line">21</span><br><span class="line">22</span><br><span class="line">23</span><br><span class="line">24</span><br></pre></td><td class="code"><pre><span class="line"><span class="comment">// DC voltage source</span></span><br><span class="line"><span class="meta">`<span class="keyword">include</span> &quot;disciplines.v&quot;</span></span><br><span class="line"><span class="keyword">module</span> vsro(p,n);</span><br><span class="line">	<span class="keyword">parameter</span> <span class="keyword">real</span> dc=O; <span class="comment">// dc voltage(V)</span></span><br><span class="line">	<span class="keyword">output</span> p,n;</span><br><span class="line">	electrical P，n；</span><br><span class="line">	</span><br><span class="line">    analog <span class="keyword">begin</span></span><br><span class="line">        V(p,n) &lt;+ dc;</span><br><span class="line">    <span class="keyword">end</span></span><br><span class="line"><span class="keyword">endmodule</span></span><br><span class="line"></span><br><span class="line"><span class="comment">// DC current source</span></span><br><span class="line">&#x27;<span class="keyword">include</span> <span class="string">&quot;disciplines.v&quot;</span></span><br><span class="line"></span><br><span class="line"><span class="keyword">module</span> isrc(p,n);</span><br><span class="line">	<span class="keyword">parameter</span> <span class="keyword">real</span> dc=O; <span class="comment">//de current(A)</span></span><br><span class="line">	<span class="keyword">output</span> p,n;</span><br><span class="line">	electrical p,n;</span><br><span class="line">    </span><br><span class="line">	analog <span class="keyword">begin</span></span><br><span class="line">        I(p,n) &lt;+ dc; </span><br><span class="line">    <span class="keyword">end</span></span><br><span class="line"><span class="keyword">endmodule</span></span><br></pre></td></tr></table></figure>

<h3 id="电路模型"><a href="#电路模型" class="headerlink" title="电路模型"></a>电路模型</h3><figure class="highlight verilog"><table><tr><td class="gutter"><pre><span class="line">1</span><br><span class="line">2</span><br><span class="line">3</span><br><span class="line">4</span><br><span class="line">5</span><br><span class="line">6</span><br><span class="line">7</span><br><span class="line">8</span><br><span class="line">9</span><br><span class="line">10</span><br><span class="line">11</span><br></pre></td><td class="code"><pre><span class="line"><span class="comment">// A simple circuit</span></span><br><span class="line"><span class="meta">`<span class="keyword">include</span> &quot;discipline.v&quot;</span></span><br><span class="line"><span class="meta">`<span class="keyword">include</span> &quot;vsrc.valilS&quot;</span></span><br><span class="line"><span class="meta">`<span class="keyword">include</span> &quot;resistor.vams&quot;</span></span><br><span class="line"></span><br><span class="line"><span class="keyword">module</span> simple_circuit;</span><br><span class="line">	electrical n;</span><br><span class="line">	ground grid;</span><br><span class="line">    vsrc <span class="variable">#(．dc(1)) V1(n，gnd)</span>;</span><br><span class="line">    resistor <span class="variable">#(．r(1k)) R1(n，gad)</span>;</span><br><span class="line"><span class="keyword">endmodule</span></span><br></pre></td></tr></table></figure>





<h2 id="参考资料"><a href="#参考资料" class="headerlink" title="参考资料"></a>参考资料</h2><ol>
<li><a target="_blank" rel="noopener" href="https://picture.iczhiku.com/resource/eetop/WyIrtTZjdTWrfMnb.pdf">基于Verilog-AMS的高速DAC高层次模型研究 (iczhiku.com)</a></li>
<li><a target="_blank" rel="noopener" href="https://www.analog-life.com/2022/04/veriloga-quick-learning/">Verilog-A 语言简单入门教程 – Analog-Life</a></li>
<li><a target="_blank" rel="noopener" href="https://designers-guide.org/verilog-ams/VlogAMS-2.4.0.pdf">Verilog-AMS Language Reference Manual (designers-guide.org)</a></li>
</ol>

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